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The product process was gradually introduced into SGT

issuing time :2022-09-29 abstract :QYnano

SGT MOSFET device scheme

A. Optimized protocell structure with the lowest epitaxial resistivity to obtain very low Rsp;

B. Adopt the self-alignment process design technology and the upper and lower structure of the primitive cell to obtain a high density of 645M/ INCH2, so as to obtain a very low Rsp;

C. Adopt advanced DFN package for better heat dissipation performance and on-resistance

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